stm32 /stm32wba5 /STM32WBA52 /PWR /PWR_WUCR3

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Interpret as PWR_WUCR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)WUSEL1 0WUSEL2 0WUSEL3 0 (B_0x0)WUSEL4 0WUSEL5 0 (B_0x0)WUSEL6 0 (B_0x0)WUSEL7 0WUSEL8

WUSEL7=B_0x0, WUSEL6=B_0x0, WUSEL1=B_0x0, WUSEL4=B_0x0

Description

PWR wakeup control register 3

Fields

WUSEL1

Wakeup and interrupt pin WKUP1 selection This field must be configured when WUPEN1 = 0. Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): WKUP1_0

1 (B_0x1): WKUP1_1

WUSEL2

Wakeup and interrupt pin WKUP2 selection This field must be configured when WUPEN2 = 0. Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

1 (B_0x1): WKUP2_1

WUSEL3

Wakeup and interrupt pin WKUP3 selection This field must be configured when WUPEN3 = 0. Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

1 (B_0x1): WKUP3_1

2 (B_0x2): WKUP3_2

WUSEL4

Wakeup and interrupt pin WKUP4 selection This field must be configured when WUPEN4 = 0. Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): WKUP4_0

1 (B_0x1): WKUP4_1

WUSEL5

Wakeup and interrupt pin WKUP5 selection This field must be configured when WUPEN5 = 0. Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

1 (B_0x1): WKUP5_1

2 (B_0x2): WKUP5_2

WUSEL6

Wakeup and interrupt pin WKUP6 selection This field must be configured when WUPEN6 = 0. Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): WKUP6_0

1 (B_0x1): WKUP6_1

3 (B_0x3): WKUP6_3 (internal source, does not generate a WKUP interrupt)

WUSEL7

Wakeup and interrupt pin WKUP7 selection This field must be configured when WUPEN7 = 0. Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): WKUP7_0

1 (B_0x1): WKUP7_1

3 (B_0x3): WKUP7_3 (internal source, does not generate a WKUP interrupt)

WUSEL8

Wakeup and interrupt pin WKUP8 selection This field must be configured when WUPEN8 = 0. Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

1 (B_0x1): WKUP8_1

2 (B_0x2): WKUP8_2

3 (B_0x3): WKUP8_3 (internal source, does not generate a WKUP interrupt)

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