SRAMER=B_0x0, WSC=B_0x0, ALE=B_0x0
RAMCFG SRAM2 control register
| ALE | SRAM2 parity fail address latch enable 0 (B_0x0): Failing address not stored in the SRAM2 parity error address register RAMCFG_M2PEAR 1 (B_0x1): Failing address stored in the SRAM2 parity error address register RAMCFG_M2PEAR |
| SRAMER | SRAM2 erase This bit can be set by software only after writing the unlock sequence in the ERASEKEY field of the RAMCFG_M2ERKEYR register. Setting this bit starts the SRAM2 erase. This bit is automatically cleared by hardware at the end of the erase operation. 0 (B_0x0): No erase operation ongoing 1 (B_0x1): Erase operation ongoing |
| WSC | SRAM2 wait state configuration This field is used to program the number of wait states inserted on the AHB when reading the SRAM2, depending on its access time. … Note: Before entering Stop 1 mode software must set SRAM2 wait states to at least 1. 0 (B_0x0): 0 wait state 1 (B_0x1): 1 wait state 7 (B_0x7): 7 wait states |