RAMCFGEN=B_0x0, GPDMA1EN=B_0x0, SRAM1EN=B_0x0, TSCEN=B_0x0, GTZC1EN=B_0x0, CRCEN=B_0x0, FLASHEN=B_0x0
RCC AHB1 peripheral clock enable register
| GPDMA1EN | GPDMA1 bus clock enable Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): GPDMA1 bus clock disabled 1 (B_0x1): GPDMA1 bus clock enabled |
| FLASHEN | FLASH bus clock enable Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): FLASH bus clock disabled 1 (B_0x1): FLASH bus clock enabled |
| CRCEN | CRC bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): CRC bus clock disabled 1 (B_0x1): CRC bus clock enabled |
| TSCEN | Touch sensing controller bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TSC bus clock disabled 1 (B_0x1): TSC bus clock enabled |
| RAMCFGEN | RAMCFG bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): RAMCFG bus clock disabled 1 (B_0x1): RAMCFG bus clock enabled |
| GTZC1EN | GTZC1 bus clock enable Set and reset by software. Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): GTZC1 bus clock disabled 1 (B_0x1): GTZC1 bus clock enabled |
| SRAM1EN | SRAM1 bus clock enable Set and reset by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SRAM1 bus clock disabled 1 (B_0x1): SRAM1 bus clock enabled |