SRAM1SMEN=B_0x0, GTZC1SMEN=B_0x0, ICACHESMEN=B_0x0, TSCSMEN=B_0x0, FLASHSMEN=B_0x0, RAMCFGSMEN=B_0x0, CRCSMEN=B_0x0, GPDMA1SMEN=B_0x0
RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
| GPDMA1SMEN | GPDMA1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): GPDMA1 bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GPDMA1 bus clock enabled by the clock gating during Sleep and Stop modes |
| FLASHSMEN | FLASH bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): FLASH bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): FLASH bus clock enabled by the clock gating during Sleep and Stop modes |
| CRCSMEN | CRC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): CRC bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): CRC bus clock enabled by the clock gating during Sleep and Stop modes |
| TSCSMEN | TSC bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV… 0 (B_0x0): TSC bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TSC bus clock enabled by the clock gating during Sleep and Stop modes |
| RAMCFGSMEN | RAMCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): RAMCFG bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): RAMCFG bus clock enabled by the clock gating during Sleep and Stop modes |
| GTZC1SMEN | GTZC1 bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): GTZC1 bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): GTZC1 bus clock enabled by the clock gating during Sleep and Stop modes |
| ICACHESMEN | ICACHE bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV… 0 (B_0x0): ICACHE bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): ICACHE bus clock enabled by the clock gating during Sleep and Stop modes |
| SRAM1SMEN | SRAM1 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SRAM1 bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM1 bus clock enabled by the clock gating during Sleep and Stop modes |