RNGSMEN=B_0x0, AESSMEN=B_0x0, GPIOCSMEN=B_0x0, SAESSMEN=B_0x0, HASHSMEN=B_0x0, PKASMEN=B_0x0, GPIOBSMEN=B_0x0, GPIOASMEN=B_0x0, SRAM2SMEN=B_0x0, GPIOHSMEN=B_0x0
RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
| GPIOASMEN | IO port A bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port A bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): IO port A bus clock enabled by the clock gating during Sleep and Stop modes |
| GPIOBSMEN | IO port B bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port B bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): IO port B bus clock enabled by the clock gating during Sleep and Stop modes |
| GPIOCSMEN | IO port C bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port C bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): IO port C bus clock enabled by the clock gating during Sleep and Stop modes |
| GPIOHSMEN | IO port H bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port H bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): IO port H bus clock enabled by the clock gating during Sleep and Stop modes |
| AESSMEN | AES bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): AES bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): AES bus clock enabled by the clock gating during Sleep and Stop modes |
| HASHSMEN | HASH bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): HASH bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): HASH bus clock enabled by the clock gating during Sleep and Stop modes |
| RNGSMEN | Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): RNG bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): RNG bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| SAESSMEN | SAES accelerator bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SAES bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SAES bus clock enabled by the clock gating during Sleep and Stop modes |
| PKASMEN | PKA bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): PKA bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): PKA bus clock enabled by the clock gating during Sleep and Stop modes |
| SRAM2SMEN | SRAM2 bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SRAM2 bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SRAM2 bus clock enabled by the clock gating during Sleep and Stop modes |