RCC_AHB4ENR

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Interpret as RCC_AHB4ENR

ADC4EN=B_0x0, PWREN=B_0x0

Description

RCC AHB4 peripheral clock enable register

Fields

PWREN

PWR bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0 (B_0x0): PWR bus clock disabled

1 (B_0x1): PWR bus clock enabled

ADC4EN

ADC4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0 (B_0x0): ADC4 bus and kernel clocks disabled

1 (B_0x1): ADC4 bus and kernel clocks enabled

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