stm32 /stm32wba5 /STM32WBA52 /RCC /RCC_APB1ENR1

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Interpret as RCC_APB1ENR1

TIM2EN=B_0x0, TIM3EN=B_0x0, I2C1EN=B_0x0, WWDGEN=B_0x0, USART2EN=B_0x0

Description

RCC APB1 peripheral clock enable register 1

Fields

TIM2EN	TIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM2 bus and kernel clocks disabled 1 (B_0x1): TIM2 bus and kernel clocks enabled
TIM3EN	TIM3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM3 bus and kernel clocks disabled 1 (B_0x1): TIM3 bus and kernel clocks enabled
WWDGEN	WWDG bus clock enable Set by software to enable the window watchdog bus clock. Reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): WWDG bus clock disabled 1 (B_0x1): WWDG bus clock enabled
USART2EN	USART2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV… 0 (B_0x0): USART2 bus and kernel clocks disabled 1 (B_0x1): USART2 bus and kernel clocks enabled
I2C1EN	I2C1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): I2C1 bus and kernel clocks disabled 1 (B_0x1): I2C1 bus and kernel clocks enabled

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