stm32 /stm32wba5 /STM32WBA52 /RCC /RCC_APB1RSTR1

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Interpret as RCC_APB1RSTR1

TIM3RST=B_0x0, I2C1RST=B_0x0, TIM2RST=B_0x0, USART2RST=B_0x0

Description

RCC APB1 peripheral reset register 1

Fields

TIM2RST	TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset TIM2
TIM3RST	TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset TIM3
USART2RST	USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset USART2
I2C1RST	I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): No effect 1 (B_0x1): Reset I2C1

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