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stm32 /stm32wba5 /STM32WBA52 /RCC /RCC_APB1RSTR2

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Interpret as RCC_APB1RSTR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LPTIM2RST

LPTIM2RST=B_0x0

Description

RCC APB1 peripheral reset register 2

Fields

LPTIM2RST

LPTIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0 (B_0x0): No effect

1 (B_0x1): Reset LPTIM2

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32