RTCAPBEN=B_0x0, LPUART1EN=B_0x0, SYSCFGEN=B_0x0, LPTIM1EN=B_0x0, SPI3EN=B_0x0, I2C3EN=B_0x0
RCC APB7 peripheral clock enable register
| SYSCFGEN | SYSCFG bus clock enable Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SYSCFG bus clock disabled 1 (B_0x1): SYSCFG bus clock enabled |
| SPI3EN | SPI3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SPI3 bus and kernel clocks disabled 1 (B_0x1): SPI3 bus and kernel clocks enabled |
| LPUART1EN | LPUART1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): LPUART1 bus and kernel clocks disabled 1 (B_0x1): LPUART1 bus and kernel clocks enabled |
| I2C3EN | I2C3 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): I2C3 bus and kernel clocks disabled 1 (B_0x1): I2C3 bus and kernel clocks enabled |
| LPTIM1EN | LPTIM1 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): LPTIM1 bus and kernel clocks disabled 1 (B_0x1): LPTIM1 bus and kernel clocks enabled |
| RTCAPBEN | RTC and TAMP bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): RTC bus clock disabled 1 (B_0x1): RTC bus clock enabled |