stm32 /stm32wba5 /STM32WBA52 /RCC /RCC_CFGR3

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Interpret as RCC_CFGR3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PPRE7

Description

RCC clock configuration register 3

Fields

PPRE7

APB7 prescaler Set and cleared by software to control the division factor of the APB7 clock (pclk7). 0xx: hclk1 not divided

4 (B_0x4): hclk1 divided by 2

5 (B_0x5): hclk1 divided by 4

6 (B_0x6): hclk1 divided by 8

7 (B_0x7): hclk1 divided by 16

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