stm32 /stm32wba5 /STM32WBA52 /SYSCFG /SYSCFG_SECCFGR

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Interpret as SYSCFG_SECCFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SYSCFGSEC 0 (B_0x0)CLASSBSEC 0 (B_0x0)FPUSEC

CLASSBSEC=B_0x0, SYSCFGSEC=B_0x0, FPUSEC=B_0x0

Description

SYSCFG secure configuration register

Fields

SYSCFGSEC

SYSCFG clock control, memory erase status and compensation cell registers security

0 (B_0x0): SYSCFG configuration clock in RCC registers, SYSCFG_MESR and SYSCFG_CCCSR, SYSCFG_CCVR and SYSCFG_CCCR can be read and written by secure and non-secure access.

1 (B_0x1): SYSCFG configuration clock in RCC registers, SYSCFG_MESR and SYSCFG_CCCSR, SYSCFG_CCVR and SYSCFG_CCCR can be read and written by secure access only.

CLASSBSEC

Class B security

0 (B_0x0): SYSCFG_CFGR2 register can be read and written by secure and non-secure access.

1 (B_0x1): SYSCFG_CFGR2 register can be read and written by secure access only.

FPUSEC

FPU security

0 (B_0x0): SYSCFG_FPUIMR register can be read and written by secure and non-secure access.

1 (B_0x1): SYSCFG_FPUIMR register can be read and written by secure access only.

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