stm32 /stm32wba5 /STM32WBA54 /RCC /RCC_PLL1DIVR

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Interpret as RCC_PLL1DIVR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL1N0 (B_0x0)PLL1P0 (B_0x0)PLL1Q0 (B_0x0)PLL1R

PLL1R=B_0x0, PLL1P=B_0x0, PLL1Q=B_0x0

Description

RCC PLL1 dividers register

Fields

PLL1N

Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). … … others: reserved VCO output frequency = Fsubref1_ck/sub x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: Multiplication factor for PLL1 VCO between 4 and 512 input frequency Fsubref1_ck/sub between 4 and 16MHz

3 (B_0x003): multiplication factor for PLL1 VCO= 4

4 (B_0x004): multiplication factor for PLL1 VCO = 5

5 (B_0x005): multiplication factor for PLL1 VCO = 6

128 (B_0x080): multiplication factor for PLL1 VCO = 129 (default after reset)

511 (B_0x1FF): multiplication factor for PLL1 VCO = 512

PLL1P

PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1pclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. …

0 (B_0x0): Not allowed

1 (B_0x1): pll1pclk = VCO output frequency / 2 (default after reset)

2 (B_0x2): not allowed

3 (B_0x3): pll1pclk = VCO output frequency / 4

127 (B_0x7F): pll1pclk = VCO output frequency / 128

PLL1Q

PLL1 DIVQ division factor Set and reset by software to control the frequency of the PLl1QCLK clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

0 (B_0x0): PLl1QCLK = VCO output frequency

1 (B_0x1): PLl1QCLK = VCO output frequency / 2 (default after reset)

2 (B_0x2): PLl1QCLK = VCO output frequency / 3

3 (B_0x3): PLl1QCLK = VCO output frequency / 4

127 (B_0x7F): PLl1QCLK = VCO output frequency / 128

PLL1R

PLL1 DIVR division factor Set and reset by software to control the frequency of the pll1rclk clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …

0 (B_0x0): pll1rclk = VCO output frequency

1 (B_0x1): pll1rclk = VCO output frequency / 2 (default after reset)

2 (B_0x2): pll1rclk = VCO output frequency / 3

3 (B_0x3): pll1rclk = VCO output frequency / 4

127 (B_0x7F): pll1rclk = VCO output frequency / 128

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