DBG_TIM3_STOP=B_0x0, DBG_IWDG_STOP=B_0x0, DBG_WWDG_STOP=B_0x0, DBG_TIM2_STOP=B_0x0, DBG_I2C1_STOP=B_0x0
DBGMCU APB1L peripheral freeze register
| DBG_TIM2_STOP | TIM2 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM2SEC. 0 (B_0x0): Normal operation. TIM2 continues to operate while CPU is in debug mode. 1 (B_0x1): Stop in debug. TIM2 is frozen while CPU is in debug mode. |
| DBG_TIM3_STOP | TIM3 stop in CPU debug Write access can be protected by GTZC_TZSC.TIM3SEC. 0 (B_0x0): Normal operation. TIM3 continues to operate while CPU is in debug mode. 1 (B_0x1): Stop in debug. TIM3 is frozen while CPU is in debug mode. |
| DBG_WWDG_STOP | WWDG stop in CPU debug Write access can be protected by GTZC_TZSC.WWDGSEC 0 (B_0x0): Normal operation. WWDG continues to operate while CPU is in debug mode. 1 (B_0x1): Stop in debug. WWDG is frozen while CPU is in debug mode. |
| DBG_IWDG_STOP | IWDG stop in CPU debug Write access can be protected by GTZC_TZSC.IWDGSEC. 0 (B_0x0): Normal operation. IWDG continues to operate while CPU is in debug mode. 1 (B_0x1): Stop in debug. IWDG is frozen while CPU is in debug mode. |
| DBG_I2C1_STOP | I2C1 SMBUS timeout stop in CPU debug Write access can be protected by GTZC_TZSC.I2C1SEC. 0 (B_0x0): Normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. 1 (B_0x1): Stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode. |