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stm32 /stm32wba5 /STM32WBA55 /DBGMCU /DBGMCU_APB7FZR

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Interpret as DBGMCU_APB7FZR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBG_I2C3_STOP 0 (B_0x0)DBG_LPTIM1_STOP 0 (B_0x0)DBG_RTC_STOP

DBG_I2C3_STOP=B_0x0, DBG_RTC_STOP=B_0x0, DBG_LPTIM1_STOP=B_0x0

Description

DBGMCU APB7 peripheral freeze register

Fields

DBG_I2C3_STOP

I2C3 stop in CPU debug

Access can be protected by GTZC_TZSC.I2C3SEC.

0 (B_0x0): Normal operation. I2C3 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. I2C3 is frozen while CPU is in debug mode.
DBG_LPTIM1_STOP

LPTIM1 stop in CPU debug

Access can be protected by GTZC_TZSC.LPTIM1SEC.

0 (B_0x0): Normal operation. LPTIM1 continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. LPTIM1 is frozen while CPU is in debug mode.
DBG_RTC_STOP

RTC stop in CPU debug

Access can be protected by GTZC_TZSC.TIM17SEC.

Can only be accessed secure when one or more features in the RTC or TAMP is/are secure.

0 (B_0x0): Normal operation. RTC continues to operate while CPU is in debug mode.

1 (B_0x1): Stop in debug. RTC is frozen while CPU is in debug mode.

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32