SRAM1_RST=B_0x0, NSWBOOT0=B_0x0, TZEN=B_0x0, SRAM2_PE=B_0x0, NBOOT0=B_0x0, IWDG_STDBY=B_0x0, NRST_STDBY=B_0x0, NRST_STOP=B_0x0, WWDG_SW=B_0x0, IWDG_SW=B_0x0, BOR_LEV=B_0x0, SRAM2_RST=B_0x0, IWDG_STOP=B_0x0
FLASH option register
| RDP | Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to Section7.6.2: Readout protection (RDP) for more details. 85 (B_0x55): Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) 170 (B_0xAA): Level 0 (readout protection not active) 204 (B_0xCC): Level 2 (chip readout protection active) |
| BOR_LEV | BOR reset level These bits contain the VsubDD/sub supply level threshold that activates/releases the reset. 0 (B_0x0): BOR level 0 (reset level threshold around 1.7V) 1 (B_0x1): BOR level 1 (reset level threshold around 2.0V) 2 (B_0x2): BOR level 2 (reset level threshold around 2.2V) 3 (B_0x3): BOR level 3 (reset level threshold around 2.5V) 4 (B_0x4): BOR level 4 (reset level threshold around 2.8V) |
| NRST_STOP | Reset generation in Stop mode 0 (B_0x0): Reset generated when entering the Stop mode 1 (B_0x1): No reset generated when entering the Stop mode |
| NRST_STDBY | Reset generation in Standby mode 0 (B_0x0): Reset generated when entering the Standby mode 1 (B_0x1): No reset generated when entering the Standby mode |
| SRAM1_RST | SRAM1 erase upon system reset 0 (B_0x0): SRAM1erased when a system reset occurs 1 (B_0x1): SRAM1 not erased when a system reset occurs |
| IWDG_SW | Independent watchdog enable selection 0 (B_0x0): Hardware mode, independent watchdog started automatically be hardware on reset selected 1 (B_0x1): Software mode, independent watchdog started by software command selected |
| IWDG_STOP | Independent watchdog counter freeze in Stop mode 0 (B_0x0): Independent watchdog counter frozen in Stop mode 1 (B_0x1): Independent watchdog counter running in Stop mode |
| IWDG_STDBY | Independent watchdog counter freeze in Standby mode 0 (B_0x0): Independent watchdog counter frozen in Standby mode 1 (B_0x1): Independent watchdog counter running in Standby mode |
| WWDG_SW | Window watchdog selection 0 (B_0x0): Hardware window watchdog selected 1 (B_0x1): Software window watchdog selected |
| SRAM2_PE | SRAM2 parity check enable 0 (B_0x0): SRAM2 parity check enabled 1 (B_0x1): SRAM2 parity check disabled |
| SRAM2_RST | SRAM2 erase when system reset 0 (B_0x0): SRAM2 erased when a system reset occurs 1 (B_0x1): SRAM2 not erased when a system reset occurs |
| NSWBOOT0 | Software BOOT0 0 (B_0x0): BOOT0 taken from the option bit NBOOT0 1 (B_0x1): BOOT0 taken from PH3/BOOT0 pin |
| NBOOT0 | NBOOT0 option bit 0 (B_0x0): NBOOT0 = 0 1 (B_0x1): NBOOT0 = 1 |
| TZEN | Global TrustZone security enable 0 (B_0x0): Global TrustZone security disabled 1 (B_0x1): Global TrustZone security enabled |