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stm32 /stm32wba5 /STM32WBA55 /GTZC1_MPCBB6 /GTZC1_MPCBB_CFGLOCK

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Interpret as GTZC1_MPCBB_CFGLOCK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SPLCK0

SPLCK0=B_0x0

Description

GTZC1 SRAMz MPCBB configuration lock register

Fields

SPLCK0

Security/privilege configuration lock super-block; This bit is set by software and can be cleared only by system reset.; note that bit [3:2] are reserved on sales type STM32WBA5xEx for MPCBB1.

0 (B_0x0): GTZC1_MPCBB_SECCFGRn and GTZC1_MPCBB_PRIVCFGRn can be written.

1 (B_0x1): Writes to GTZC1_MPCBB_SECCFGRn and GTZC1_MPCBB_PRIVCFGRn are ignored

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32