GTZC1_TZSC_SECCFGR2

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Interpret as GTZC1_TZSC_SECCFGR2

COMPSEC=B_0x0, LPTIM1SEC=B_0x0, SPI1SEC=B_0x0, ADC4SEC=B_0x0, I2C3SEC=B_0x0, SPI3SEC=B_0x0, USART1SEC=B_0x0, LPUART1SEC=B_0x0, TIM16SEC=B_0x0, TIM17SEC=B_0x0, TIM1SEC=B_0x0

Description

GTZC1 TZSC secure configuration register 2

Fields

TIM1SEC	secure access mode for TIM1 0 (B_0x0): non-secure 1 (B_0x1): secure
SPI1SEC	secure access mode for SPI1 0 (B_0x0): non-secure 1 (B_0x1): secure
USART1SEC	secure access mode for USART1 0 (B_0x0): non-secure 1 (B_0x1): secure
TIM16SEC	secure access mode for TIM16 0 (B_0x0): non-secure 1 (B_0x1): secure
TIM17SEC	secure access mode for TIM17 0 (B_0x0): non-secure 1 (B_0x1): secure
SPI3SEC	secure access mode for SPI3 0 (B_0x0): non-secure 1 (B_0x1): secure
LPUART1SEC	secure access mode for LPUART1 0 (B_0x0): non-secure 1 (B_0x1): secure
I2C3SEC	secure access mode for I2C3 0 (B_0x0): non-secure 1 (B_0x1): secure
LPTIM1SEC	secure access mode for LPTIM1 0 (B_0x0): non-secure 1 (B_0x1): secure
COMPSEC	secure access mode for COMP Note that bit 23 is reserved on sales type STM32WBA52. 0 (B_0x0): non-secure 1 (B_0x1): secure
ADC4SEC	secure access mode for ADC4 0 (B_0x0): non-secure 1 (B_0x1): secure

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