MODE=B_0x0, LKEY=B_0x0, MDMAT=B_0x0, DMAE=B_0x0, DATATYPE=B_0x0, ALGO=B_0x0
HASH control register
| INIT | Initialize message digest calculation Writing this bit to 1 resets the hash processor core, so that the HASH is ready to compute the message digest of a new message. Writing this bit to 0 has no effect. Reading this bit always return 0. |
| DMAE | DMA enable After this bit is set it is cleared by hardware while the last data of the message is written into the hash processor. Setting this bit to 0 while a DMA transfer is ongoing is not aborting this current transfer. Instead, the DMA interface of the IP remains internally enabled until the transfer is completed or INIT is written to 1. Setting INIT bit to 1 does not clear DMAE bit. 0 (B_0x0): DMA transfers disabled 1 (B_0x1): DMA transfers enabled. A DMA request is sent as soon as the HASH core is ready to receive data. |
| DATATYPE | Data type selection Defines the format of the data entered into the HASH_DIN register: 0 (B_0x0): 32-bit data. The data written into HASH_DIN are directly used by the HASH processing, without reordering. 1 (B_0x1): 16-bit data, or half-word. The data written into HASH_DIN are considered as two half-words, and are swapped before being used by the HASH processing. 2 (B_0x2): 8-bit data, or bytes. The data written into HASH_DIN are considered as four bytes, and are swapped before being used by the HASH processing. 3 (B_0x3): bit data, or bit-string. The data written into HASH_DIN are considered as 32 bits (1st bit of the string at position 0), and are swapped before being used by the HASH processing (1st bit of the string at position 31). |
| MODE | Mode selection This bit selects the HASH or HMAC mode for the selected algorithm: This selection is only taken into account when the INIT bit is set. Changing this bit during a computation has no effect. 0 (B_0x0): Hash mode selected 1 (B_0x1): HMAC mode selected. LKEY must be set if the key being used is longer than 64 bytes. |
| NBW | Number of words already pushed Refer to NBWP[3:0] bitfield of HASH_SR for the description. This bitfield is read-only. |
| DINNE | DIN not empty Refer to DINNE bit of HASH_SR for the description. This bit is read-only. |
| MDMAT | Multiple DMA transfers This bit is set when hashing large files when multiple DMA transfers are needed. 0 (B_0x0): DCAL is automatically set at the end of a DMA transfer. 1 (B_0x1): DCAL is not automatically set at the end of a DMA transfer. |
| LKEY | Long key selection This bit selects between short key (less than or equal 64 bytes) or long key ( 64 bytes) in HMAC mode. This selection is only taken into account when the INIT and MODE bits are both set. Changing this bit during a computation has no effect. 0 (B_0x0): the HMAC key is shorter or equal to 64 bytes. The actual key value written to HASH_DIN is used during the HMAC computation. 1 (B_0x1): the HMAC key is longer than 64 bytes. The hash of the key is used instead of the real key during the HMAC computation. |
| ALGO | Algorithm selection These bits select the hash algorithm. This selection is only taken into account when the INIT bit is set. Changing this bitfield during a computation has no effect. When ALGO bitfield is updated and INIT bit is set, NBWE in HASH_SR is automatically updated to 0x11. 0 (B_0x0): SHA-1 1 (B_0x1): MD5 2 (B_0x2): SHA2-224 3 (B_0x3): SHA2-256 |