PR=B_0x0
IWDG prescaler register
PR | Prescaler divider These bits are write access protected see Section 29.4.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of the IWDG status register (IWDG_SR) must be reset in order to be able to change the prescaler divider. Others: divider / 1024 Note: Reading this register returns the prescaler value from the VsubDD/sub voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG status register (IWDG_SR) is reset. 0 (B_0x0): divider / 4 1 (B_0x1): divider / 8 2 (B_0x2): divider / 16 3 (B_0x3): divider / 32 4 (B_0x4): divider / 64 5 (B_0x5): divider / 128 6 (B_0x6): divider / 256 7 (B_0x7): divider / 512 |