R1RSB1=B_0x0, R2RSB1=B_0x0, RADIORSB=B_0x0, ULPMEN=B_0x0, LPMS=B_0x0
PWR control register 1
| LPMS | Low-power mode selection These bits select the low-power mode entered when the CPU enters the SleepDeep mode. 10x: Standby mode others reserved 0 (B_0x0): Stop 0 mode 1 (B_0x1): Stop 1 mode |
| R2RSB1 | SRAM2 retention in Standby mode This bit is used to keep the SRAM2 content in Standby retention mode. 0 (B_0x0): SRAM2 content not retained in Standby mode 1 (B_0x1): SRAM2 content retained in Standby mode |
| ULPMEN | BOR0 ultra-low-power mode. This bit is used to reduce the consumption by configuring the BOR0 in discontinuous mode for Stop 1 and Standby modes. Discontinuous mode is only available when BOR levels 1 to 4 and PVD are disabled. Note: This bit must be set to reach the lowest power consumption in the low-power modes. Note: This bit must not be set together with autonomous peripherals using HSI16 as kernel clock. Note: When BOR level 1 to 4 or PVD is enabled continuous mode applies independent from ULPMEN. 0 (B_0x0): BOR0 operating in continuous (normal) mode in all operating modes 1 (B_0x1): BOR0 operating in discontinuous (ultra-low-power) mode in Stop 1 and Standby modes. |
| RADIORSB | 2.4 GHz RADIO SRAMs (RXTXRAM and Sequence RAM) and Sleep clock retention in Standby mode. This bit is used to keep the 2.4 GHz RADIO SRAMs content in Standby retention mode and the 2.4 GHz RADIO sleep timer counter operational. 0 (B_0x0): 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode 1 (B_0x1): 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode |
| R1RSB1 | SRAM1 retention in Standby mode This bit is used to keep the SRAM1 content in Standby retention mode. 0 (B_0x0): SRAM1 content not retained in Standby mode 1 (B_0x1): SRAM1 content retained in Standby mode |