RegViz: Visualize PWR_IORETENRA Bitfield

stm32 /stm32wba5 /STM32WBA55 /PWR /PWR_IORETENRA

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Interpret as PWR_IORETENRA

EN13=B_0x0, EN12=B_0x0, EN11=B_0x0, EN5=B_0x0, EN10=B_0x0, EN6=B_0x0, EN7=B_0x0, EN9=B_0x0, EN14=B_0x0, EN8=B_0x0, EN15=B_0x0

Description

PWR port A Standby IO retention enable register

Fields

EN0	Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy
EN1	Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy
EN2	Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy
EN3	Port A Standby GPIO retention enable Access can be protected by GPIOA SECy, privilege protection is controlled by PWR SPRIV or PWR NSPRIV. When set, each bit enables the Standby GPIO retention feature for PAy
EN5	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN6	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN7	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN8	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN9	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN10	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN11	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN12	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN13	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN14	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.
EN15	Port A Standby GPIO retention enable Access can be secured by GPIOA SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PAy Standby GPIO retention feature disabled. 1 (B_0x1): PAy Standby GPIO retention feature enabled.

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