stm32 /stm32wba5 /STM32WBA55 /PWR /PWR_IORETENRC

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Interpret as PWR_IORETENRC

EN13=B_0x0, EN15=B_0x0, EN14=B_0x0

Description

PWR port C Standby IO retention enable register

Fields

EN13	Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PCy Standby GPIO retention feature disabled. 1 (B_0x1): PCy Standby GPIO retention feature enabled.
EN14	Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PCy Standby GPIO retention feature disabled. 1 (B_0x1): PCy Standby GPIO retention feature enabled.
EN15	Port C Standby GPIO retention enable Access can be secured by GPIOC SECy. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. 0 (B_0x0): PCy Standby GPIO retention feature disabled. 1 (B_0x1): PCy Standby GPIO retention feature enabled.

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