STOPF=B_0x0, SBF=B_0x0
PWR status register
| CSSF | Clear Stop and Standby flags Access can be secured by PWR LPMSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV. Writing 1 to this bit clears the STOPF and SBF flags. |
| STOPF | Stop flag This bit is set by hardware when the device enters a Stop or Standby mode at the same time as the sysclk has been set by hardware to select HSI16. It’s cleared by software by writing 1 to the CSSF bit and by hardware when SBF is set. 0 (B_0x0): The device did not enter any Stop mode. 1 (B_0x1): The device entered a Stop mode. |
| SBF | Standby flag This bit is set by hardware when the device enters the Standby mode and the CPU restart from its reset vector. It’s cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 0 (B_0x0): The device did not enter Standby mode. 1 (B_0x1): The device entered Standby mode. |