stm32 /stm32wba5 /STM32WBA55 /PWR /PWR_WUCR1

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Interpret as PWR_WUCR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)WUPEN1 0 (B_0x0)WUPEN2 0 (B_0x0)WUPEN3 0 (B_0x0)WUPEN4 0 (B_0x0)WUPEN5 0 (B_0x0)WUPEN6 0 (B_0x0)WUPEN7 0 (B_0x0)WUPEN8

WUPEN6=B_0x0, WUPEN2=B_0x0, WUPEN1=B_0x0, WUPEN7=B_0x0, WUPEN4=B_0x0, WUPEN3=B_0x0, WUPEN5=B_0x0, WUPEN8=B_0x0

Description

PWR wakeup control register 1

Fields

WUPEN1

Wakeup and interrupt pin WKUP1 enable Access can be secured by PWR WUP1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP1 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP1 enabled

WUPEN2

Wakeup and interrupt pin WKUP2 enable Access can be secured by PWR WUP2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP2 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP2 enabled

WUPEN3

Wakeup and interrupt pin WKUP3 enable Access can be secured by PWR WUP3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP3 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP3 enabled

WUPEN4

Wakeup and interrupt pin WKUP4 enable Access can be secured by PWR WUP4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP4 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP4 enabled

WUPEN5

Wakeup and interrupt pin WKUP5 enable Access can be secured by PWR WUP5SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP5 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP5 enabled

WUPEN6

Wakeup and interrupt pin WKUP6 enable Access can be secured by PWR WUP6SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP6 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP6 enabled

WUPEN7

Wakeup and interrupt pin WKUP7 enable Access can be secured by PWR WUP7SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP7 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP7 enabled

WUPEN8

Wakeup and interrupt pin WKUP8 enable Access can be secured by PWR WUP8SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with PWR SPRIV or when non-secure with PWR NSPRIV.

0 (B_0x0): Wakeup and interrupt pin WKUP8 disabled

1 (B_0x1): Wakeup and interrupt pin WKUP8 enabled

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