HASHEN=B_0x0, GPIOAEN=B_0x0, GPIOCEN=B_0x0, SRAM2EN=B_0x0, PKAEN=B_0x0, HSEMEN=B_0x0, AESEN=B_0x0, GPIOHEN=B_0x0, RNGEN=B_0x0, SAESEN=B_0x0, GPIOBEN=B_0x0
RCC AHB2 peripheral clock enable register
| GPIOAEN | IO port A bus clock enable Set and cleared by software. Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port A bus clock disabled 1 (B_0x1): IO port A bus clock enabled |
| GPIOBEN | IO port B bus clock enable Set and cleared by software. Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port B bus clock disabled 1 (B_0x1): IO port B bus clock enabled |
| GPIOCEN | IO port C bus clock enable Set and cleared by software. Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port C bus clock disabled 1 (B_0x1): IO port C bus clock enabled |
| GPIOHEN | IO port H bus clock enable Set and cleared by software. Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): IO port H bus clock disabled 1 (B_0x1): IO port H bus clock enabled |
| AESEN | AES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): AES bus clock disabled 1 (B_0x1): AES bus clock enabled |
| HASHEN | HASH bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): HASH bus clock disabled 1 (B_0x1): HASH bus clock enabled |
| RNGEN | RNG bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): RNG bus and kernel clocks disabled 1 (B_0x1): RNG bus and kernel clocks enabled |
| SAESEN | SAES bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SAES bus clock disabled 1 (B_0x1): SAES bus clock enabled |
| HSEMEN | HSEM bus clock enable Set and cleared by software. Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): HSEM bus clock disabled 1 (B_0x1): HSEM bus clock enabled |
| PKAEN | PKA bus clock enable Set and cleared by software. Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): PKA bus clock disabled 1 (B_0x1): PKA bus clock enabled |
| SRAM2EN | SRAM2 bus clock enable Set and cleared by software. Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SRAM2 bus clock disabled 1 (B_0x1): SRAM2 bus clock enabled |