RCC_APB1SMENR2

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Interpret as RCC_APB1SMENR2

LPTIM2SMEN=B_0x0

Description

RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2

Fields

LPTIM2SMEN

LPTIM2 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.

0 (B_0x0): LPTIM2 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes

1 (B_0x1): LPTIM2 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes

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