TIM17SMEN=B_0x0, TIM16SMEN=B_0x0, USART1SMEN=B_0x0, SPI1SMEN=B_0x0, TIM1SMEN=B_0x0
RCC APB2 peripheral clocks enable in Sleep and Stop modes register
| TIM1SMEN | TIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| SPI1SMEN | SPI1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): SPI1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SPI1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| USART1SMEN | USART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): USART1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): USART1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| TIM16SMEN | TIM16 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM16 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM16 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| TIM17SMEN | TIM17 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): TIM17 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): TIM17 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |