I2C3SMEN=B_0x0, SPI3SMEN=B_0x0, LPTIM1SMEN=B_0x0, LPUART1SMEN=B_0x0, RTCAPBSMEN=B_0x0, SYSCFGSMEN=B_0x0
RCC APB7 peripheral clock enable in Sleep and Stop modes register
| SYSCFGSMEN | SYSCFG bus clock enable during Sleep and Stop modes Set and cleared by software. Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. 0 (B_0x0): SYSCFG bus clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SYSCFG bus clock enabled by the clock gating during Sleep and Stop modes |
| SPI3SMEN | SPI3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): SPI3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): SPI3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| LPUART1SMEN | LPUART1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): LPUART1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPUART1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| I2C3SMEN | I2C3 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): I2C3 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): I2C3 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| LPTIM1SMEN | LPTIM1 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): LPTIM1 bus and kernel clocks disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): LPTIM1 bus and kernel clocks enabled by the clock gating during Sleep and Stop modes |
| RTCAPBSMEN | RTC and TAMP APB clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 (B_0x0): RTC and TAMP APB clock disabled by the clock gating during Sleep and Stop modes 1 (B_0x1): RTC and TAMP APB clock enabled by the clock gating during Sleep and Stop modes |