stm32 /stm32wba5 /STM32WBA55 /RCC /RCC_CSR

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Interpret as RCC_CSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)RMVF 0 (B_0x0)OBLRSTF 0 (B_0x0)PINRSTF 0 (B_0x0)BORRSTF 0 (B_0x0)SFTRSTF 0 (B_0x0)IWDGRSTF 0 (B_0x0)WWDGRSTF 0 (B_0x0)LPWRRSTF

RMVF=B_0x0, IWDGRSTF=B_0x0, LPWRRSTF=B_0x0, OBLRSTF=B_0x0, SFTRSTF=B_0x0, WWDGRSTF=B_0x0, BORRSTF=B_0x0, PINRSTF=B_0x0

Description

RCC control/status register

Fields

RMVF

Remove reset flag Set by software to clear the reset flags. Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.

0 (B_0x0): No effect

1 (B_0x1): Clear the reset flags (once set by software bit is cleared automatically by hardware)

OBLRSTF

Option byte loader reset flag Set by hardware when a reset from the option byte loading occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): No reset from option byte loading occurred

1 (B_0x1): Reset from option byte loading occurred

PINRSTF

NRST pin reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): No reset from NRST pin occurred

1 (B_0x1): Reset from NRST pin occurred

BORRSTF

BOR flag Set by hardware when a BOR occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): no BOR occurred

1 (B_0x1): BOR occurred

SFTRSTF

Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): no software reset occurred

1 (B_0x1): software reset occurred

IWDGRSTF

Independent watchdog reset flag Set by hardware when an independent watchdog reset domain occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): no independent watchdog reset occurred

1 (B_0x1): independent watchdog reset occurred

WWDGRSTF

Window watchdog reset flag Set by hardware when a window watchdog reset occurs. Cleared by writing to the RMVF bit.

0 (B_0x0): no window watchdog reset occurred

1 (B_0x1): window watchdog reset occurred

LPWRRSTF

Low-power reset flag Set by hardware when a reset occurs due to illegal Stop and Standby modes entry. Cleared by writing to the RMVF bit.

0 (B_0x0): no illegal mode reset occurred

1 (B_0x1): illegal mode reset occurred

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