SAES_IVR0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SAES_IVR0

Description

SAES initialization vector register 0

Fields

IVI

Initialization vector input, bits [31:0] SAES_IVRx registers store the 128-bit initialization vector or the nonce, depending on the chaining mode selected. This value is updated by the AES core after each computation round (when applicable). Write to this register is ignored when EN bit is set in SAES_SR register

Links

()