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stm32 /stm32wl /STM32WL5x_CM0P /DAC /CR

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Interpret as CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN1)EN1 0 (TEN1)TEN1 0 (TSEL10)TSEL10 0 (TSEL11)TSEL11 0 (TSEL12)TSEL12 0 (TSEL13)TSEL13 0WAVE1 0MAMP10 (DMAEN1)DMAEN1 0 (DMAUDRIE1)DMAUDRIE1 0 (CEN1)CEN1

Description

control register

Fields

EN1

DAC channel1 enable
TEN1

DAC channel1 trigger enable
TSEL10

TSEL10
TSEL11

TSEL11
TSEL12

TSEL12
TSEL13

DAC channel1 trigger selection
WAVE1

DAC channel1 noise/triangle wave generation enable
MAMP1

DAC channel1 mask/amplitude selector
DMAEN1

DAC channel1 DMA enable
DMAUDRIE1

DAC channel1 DMA Underrun Interrupt enable
CEN1

DAC Channel 1 calibration enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32