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stm32 /stm32wl /STM32WL5x_CM0P /FLASH /C2ACR

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Interpret as C2ACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PRFTEN)PRFTEN 0 (ICEN)ICEN 0 (ICRST)ICRST 0 (PES)PES

Description

Flash CPU2 access control register

Fields

PRFTEN

CPU2 Prefetch enable
ICEN

CPU2 Instruction cache enable
ICRST

CPU2 Instruction cache reset
PES

CPU2 program / erase suspend request

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32