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stm32 /stm32wl /STM32WL5x_CM0P /LPUART /ISR_enabled

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Interpret as ISR_enabled

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PE)PE 0 (FE)FE 0 (NE)NE 0 (ORE)ORE 0 (IDLE)IDLE 0 (RXFNE)RXFNE 0 (TC)TC 0 (TXFNF)TXFNF 0 (CTSIF)CTSIF 0 (CTS)CTS 0 (BUSY)BUSY 0 (CMF)CMF 0 (SBKF)SBKF 0 (RWU)RWU 0 (WUF)WUF 0 (TEACK)TEACK 0 (REACK)REACK 0 (TXFE)TXFE 0 (RXFF)RXFF 0 (RXFT)RXFT 0 (TXFT)TXFT

Description

Interrupt and status register

Fields

PE

PE
FE

FE
NE

NE
ORE

ORE
IDLE

IDLE
RXFNE

RXFNE
TC

TC
TXFNF

TXFNF
CTSIF

CTSIF
CTS

CTS
BUSY

BUSY
CMF

CMF
SBKF

SBKF
RWU

RWU
WUF

WUF
TEACK

TEACK
REACK

REACK
TXFE

TXFIFO Empty
RXFF

RXFIFO Full
RXFT

RXFIFO threshold flag
TXFT

TXFIFO threshold flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32