stm32 /stm32wl /STM32WL5x_CM0P /PWR /C2CR1

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Interpret as C2CR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LPMS0 (FPDR)FPDR 0 (FPDS)FPDS

Description

Power CPU2 control register 1 [dual core device only]

Fields

LPMS

Low-power mode selection for CPU2

FPDR

Flash memory power down mode during LPRun for CPU2

FPDS

Flash memory power down mode during LPSleep for CPU2

Links

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