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stm32 /stm32wl /STM32WL5x_CM0P /PWR /SCR

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Interpret as SCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CWUF1)CWUF1 0 (CWUF2)CWUF2 0 (CWUF3)CWUF3 0 (CWPVDF)CWPVDF 0 (CWRFBUSYF)CWRFBUSYF 0 (CC2HF)CC2HF

Description

Power status clear register

Fields

CWUF1

Clear wakeup flag 1
CWUF2

Clear wakeup flag 2
CWUF3

Clear wakeup flag 3
CWPVDF

Clear wakeup PVD interrupt flag
CWRFBUSYF

Clear wakeup Radio BUSY flag
CC2HF

lear CPU2 Hold interrupt flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32