stm32 /stm32wl /STM32WL5x_CM0P /RCC /AHB3SMENR

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Interpret as AHB3SMENR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PKASMEN)PKASMEN 0 (AESSMEN)AESSMEN 0 (RNGSMEN)RNGSMEN 0 (SRAM1SMEN)SRAM1SMEN 0 (SRAM2SMEN)SRAM2SMEN 0 (FLASHSMEN)FLASHSMEN

Description

AHB3 peripheral clocks enable in Sleep and Stop modes register

Fields

PKASMEN

PKA accelerator clock enable during CPU1 CSleep mode.

AESSMEN

AES accelerator clock enable during CPU1 CSleep mode.

RNGSMEN

True RNG clocks enable during CPU1 Csleep and CStop modes

SRAM1SMEN

SRAM1 interface clock enable during CPU1 CSleep mode.

SRAM2SMEN

SRAM2 memory interface clock enable during CPU1 CSleep mode

FLASHSMEN

Flash interface clock enable during CPU1 CSleep mode.

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