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stm32 /stm32wl /STM32WL5x_CM0P /RCC /CIFR

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Interpret as CIFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LSIRDYF)LSIRDYF 0 (LSERDYF)LSERDYF 0 (MSIRDYF)MSIRDYF 0 (HSIRDYF)HSIRDYF 0 (HSERDYF)HSERDYF 0 (PLLRDYF)PLLRDYF 0 (CSSF)CSSF 0 (LSECSSF)LSECSSF

Description

Clock interrupt flag register

Fields

LSIRDYF

LSI ready interrupt flag
LSERDYF

LSE ready interrupt flag
MSIRDYF

MSI ready interrupt flag
HSIRDYF

HSI16 ready interrupt flag
HSERDYF

HSE32 ready interrupt flag
PLLRDYF

PLL ready interrupt flag
CSSF

HSE32 Clock security system interrupt flag
LSECSSF

LSE Clock security system interrupt flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32