Regviz

stm32 /stm32wl /STM32WL5x_CM0P /RCC /ICSCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ICSCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/RCC/ICSCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MSICAL0MSITRIM0HSICAL0HSITRIM

Description

Internal clock sources calibration register

Fields

MSICAL

MSI clock calibration
MSITRIM

MSI clock trimming
HSICAL

HSI16 clock calibration
HSITRIM

HSI16 clock trimming

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32