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stm32 /stm32wl /STM32WL5x_CM0P /TIM1 /CCER

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Interpret as CCER

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM4/TIM1/CCER#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC1E)CC1E 0 (CC1P)CC1P 0 (CC1NE)CC1NE 0 (CC1NP)CC1NP 0 (CC2E)CC2E 0 (CC2P)CC2P 0 (CC2NE)CC2NE 0 (CC2NP)CC2NP 0 (CC3E)CC3E 0 (CC3P)CC3P 0 (CC3NE)CC3NE 0 (CC3NP)CC3NP 0 (CC4E)CC4E 0 (CC4P)CC4P 0 (CC5E)CC5E 0 (CC5P)CC5P 0 (CC6E)CC6E 0 (CC6P)CC6P

Description

capture/compare enable register

Fields

CC1E

CC1E
CC1P

CC1P
CC1NE

CC1NE
CC1NP

CC1NP
CC2E

CC2E
CC2P

CC2P
CC2NE

CC2NE
CC2NP

CC2NP
CC3E

CC3E
CC3P

CC3P
CC3NE

CC3NE
CC3NP

CC3NP
CC4E

CC4E
CC4P

CC4P
CC5E

CC5E
CC5P

CC5P
CC6E

CC6E
CC6P

CC6P

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32