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stm32 /stm32wl /STM32WL5x_CM0P /TIM16 /CCER

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Interpret as CCER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC1E)CC1E 0 (CC1P)CC1P 0 (CC1NE)CC1NE 0 (CC1NP)CC1NP

Description

TIM16/TIM17 capture/compare enable register

Fields

CC1E

Capture/Compare 1 output enable
CC1P

Capture/Compare 1 output polarity
CC1NE

Capture/Compare 1 complementary output enable
CC1NP

Capture/Compare 1 complementary output polarity

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32