stm32 /stm32wl /STM32WL5x_CM4 /DAC /SHRR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SHRR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TREFRESH1

Description

Sample and Hold refresh time register

Fields

TREFRESH1

DAC Channel 1 refresh Time (only valid in Sample and Hold mode)

Links

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