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stm32 /stm32wl /STM32WL5x_CM4 /DMAMUX /CSR

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Interpret as CSR

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/DMAMUX/CSR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SOF0)SOF0 0 (SOF1)SOF1 0 (SOF2)SOF2 0 (SOF3)SOF3 0 (SOF4)SOF4 0 (SOF5)SOF5 0 (SOF6)SOF6 0 (SOF7)SOF7 0 (SOF8)SOF8 0 (SOF9)SOF9 0 (SOF10)SOF10 0 (SOF11)SOF11 0 (SOF12)SOF12 0 (SOF13)SOF13

Description

request line multiplexer interrupt channel status register

Fields

SOF0

SOF0
SOF1

SOF1
SOF2

SOF2
SOF3

SOF3
SOF4

SOF4
SOF5

SOF5
SOF6

SOF6
SOF7

SOF7
SOF8

SOF8
SOF9

SOF9
SOF10

SOF10
SOF11

SOF11
SOF12

SOF12
SOF13

Synchronization overrun event flag

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32