Regviz

stm32 /stm32wl /STM32WL5x_CM4 /LPTIM2 /CFGR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CFGR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/LPTIM2/CFGR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CKSEL)CKSEL 0CKPOL 0CKFLT 0TRGFLT 0PRESC0TRIGSEL 0TRIGEN 0 (TIMOUT)TIMOUT 0 (WAVE)WAVE 0 (WAVPOL)WAVPOL 0 (PRELOAD)PRELOAD 0 (COUNTMODE)COUNTMODE 0 (ENC)ENC

Description

configuration register

Fields

CKSEL

CKSEL
CKPOL

CKPOL
CKFLT

CKFLT
TRGFLT

TRGFLT
PRESC

PRESC
TRIGSEL

TRIGSEL
TRIGEN

TRIGEN
TIMOUT

TIMOUT
WAVE

WAVE
WAVPOL

WAVPOL
PRELOAD

PRELOAD
COUNTMODE

COUNTMODE
ENC

ENC

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32