stm32 /stm32wl /STM32WL5x_CM4 /RCC /CFGR

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Interpret as CFGR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SW0SWS0HPRE0PPRE10PPRE20 (STOPWUCK)STOPWUCK 0 (HPREF)HPREF 0 (PPRE1F)PPRE1F 0 (PPRE2F)PPRE2F 0MCOSEL0MCOPRE

Description

Clock configuration register

Fields

SW

System clock switch

SWS

System clock switch status

HPRE

HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)

PPRE1

PCLK1 low-speed prescaler (APB1)

PPRE2

PCLK2 high-speed prescaler (APB2)

STOPWUCK

Wakeup from Stop and CSS backup clock selection

HPREF

HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1)

PPRE1F

PCLK1 prescaler flag (APB1)

PPRE2F

PCLK2 prescaler flag (APB2)

MCOSEL

Microcontroller clock output

MCOPRE

Microcontroller clock output prescaler

Links

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