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stm32 /stm32wl /STM32WL5x_CM4 /RTC /MISR

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Interpret as MISR

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https://regviz.com/r/stm32/stm32wl/STM32WL5x_CM0P/RTC/MISR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALRAMF)ALRAMF 0 (ALRBMF)ALRBMF 0 (WUTMF)WUTMF 0 (TSMF)TSMF 0 (TSOVMF)TSOVMF 0 (ITSMF)ITSMF 0 (SSRUMF)SSRUMF

Description

MISR

Fields

ALRAMF

Alarm A masked flag
ALRBMF

Alarm B masked flag
WUTMF

Wakeup timer masked flag
TSMF

Timestamp masked flag
TSOVMF

Timestamp overflow masked flag
ITSMF

Internal timestamp masked flag
SSRUMF

SSR underflow masked flag

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32