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stm32 /stm32wl /STM32WL5x_CM4 /TIM1 /AF1

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Interpret as AF1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (BKINE)BKINE 0 (BKCMP1E)BKCMP1E 0 (BKCMP2E)BKCMP2E 0 (BKINP)BKINP 0 (BKCMP1P)BKCMP1P 0 (BKCMP2P)BKCMP2P 0ResETRSEL

Description

alternate function option register 1

Fields

BKINE

BRK BKIN input enable
BKCMP1E

BRK COMP1 enable
BKCMP2E

BRK COMP2 enable
BKINP

BRK BKIN input polarity
BKCMP1P

BRK COMP1 input polarity
BKCMP2P

BRK COMP2 input polarity
ResETRSEL

ETR source selection

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32