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stm32 /stm32wl /STM32WL5x_CM4 /TIM1 /EGR

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Interpret as EGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UG)UG 0 (CC1G)CC1G 0 (CC2G)CC2G 0 (CC3G)CC3G 0 (CC4G)CC4G 0 (COM)COM 0 (TG)TG 0 (BG)BG 0 (B2G)B2G

Description

event generation register

Fields

UG

Update generation
CC1G

Capture/Compare 1 generation
CC2G

Capture/Compare 2 generation
CC3G

Capture/Compare 3 generation
CC4G

Capture/Compare 4 generation
COM

Capture/Compare control update generation
TG

Trigger generation
BG

Break generation
B2G

Break 2 generation

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32