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stm32 /stm32wl /STM32WL5x_CM4 /TIM1 /TISEL

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Interpret as TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TI1SEL0TI2SEL0TI3SEL0TI4SEL

Description

timer input selection register

Fields

TI1SEL

selects TI1[0] to TI1[15] input
TI2SEL

selects TI2[0] to TI2[15] input
TI3SEL

selects TI3[0] to TI3[15] input
TI4SEL

selects TI4[0] to TI4[15] input

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32