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stm32 /stm32wl /STM32WL5x_CM4 /TIM16 /CCMR1_Input

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Interpret as CCMR1_Input

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CC1S 0IC1PSC 0IC1F

Description

TIM16/TIM17 capture/compare mode register 1

Fields

CC1S

CC1S
IC1PSC

IC1PSC
IC1F

IC1F

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32